C-DAC Thiruvananthapuram Recruitment for the Project Engineer

Recruitment for the Project Engineer

Eligibility : ME/M.Tech(CSE, ECE), BE/B.Tech(CSE, EEE, ECE, Electrical)
 
Location : Thiruvananthapuram

Job Category : Core Technical, Govt Sector

Last Date : 23 Sep 2013

Job Type : Full Time

Hiring Process : Face to Face Interview




Advt. No. CDAC (T)/RCT/52/2013 dated 11.09.2013

Centre Development of Advanced Computing (C-DAC ) Thiruvananthapuram invites applications for the posts of Project Engineer on Contract Basis 

Post No	Name of the Post	Branch/Discipline	No. of Posts	Qualification	Pay Scale	Age Limit
52.1.1	Project Engineer-I	Electronics	13	1st Class with 70% marks in B.E./B.Tech in Electronics & Communications Engineering. For SC/ST Candidates 1st Class with 60% marks	Rs. 26,500	30 years
52.1.2		Computer Science	13	1st Class with 70% marks in B.E. / B.Tech in Computer Science & Engineering. For SC/ST Candidates 1st Class with 60% marks.
52.1.3		Electrical	03	1st Class with 70% marks in B.E. / B.Tech in Electrical Engineering / Electrical & Electronics Engineering. For SC/ST Candidates 1st Class with 60% marks.
52.2.1	Project Engineer-II	Electronics	03	1st Class with 70% marks in M.E. / M.Tech in Electronics Engineering. For SC/ST Candidates 1st Class with 60% Marks. Desirable exposure required for the post : RF systems. High speed digital hardware design for embedded systems. Digital signal processing and digital communications - simulation & implementation. FPGA based system design (preferably for wireless/telecom applications.) Design and implementation of communication protocol stack.	Rs. 32,100	32 years
52.2.2		VLSI & Embedded System	02	1st Class with 70% marks in M.E. / M.Tech in VLSI & Embedded System. For SC/ST Candidates 1st Class with 60% Marks. Desirable exposure required for the post :   Experience in CMOS Analog IC design. CMOS circuit simulation and layout. Familiarity in using EDA design tools like Spectre, Virtuoso and Assura. Experience in writing and debugging analog behavioral models using Verilog-A  Experience in System design and modeling using Cadence Spectre.
52.2.3		Computer Science	02	1st Class with 70% marks in M.E. / M.Tech in Computer Science & Engineering. For SC/ST Candidates 1st Class with 60% marks.
52.2.4		Electrical	04	1st Class with 70% marks in M.E. / M.Tech in any Electrical Power / Control Discipline. For SC/ST Candidates 1st Class with 60% marks. (Specialization in Power Electronics/ Electrical Drives/ Power Systems and Control are Preferable).
52.2.5		Computational Linguistic	02	1st Class with 70% marks in M.E. / M.Tech in Computational Linguistic & Engineering. For SC/STCandidates 1st Class with 60% marks.

Selection : i) Initial screening will be based on academic records. The minimum eligibility for applying will be 1st Class with 70% marks in the qualifying examination (For SC/ST Candidates 1st Class with 60% marks). Short listed candidates will be called for Test and Multilevel Interview. The exact Date, time and venue of the Test and Interview will be intimated separately through e-mail/letter by post.

How to apply

Candidates should apply Online. Online submission closes on September 23, 2013 at 12.00 midnight. 

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